Caltech Nanofabrication Group

We developed an underetching technique to define submicrometer channel length polymer field-effect transistors. Short-channel effects are avoided by using thin silicon dioxide as gate insulator. The transistors with 1 and 0.74 µm channel length operate at a voltage as low as 5 V with a low inverse subthreshold slope of 0.4–0.5 V/dec, on–off ratio of 104, and without short-channel effects. The poly(3-alcylthiophene)'s still suffer from a low mobility and hysteresis does occur, but it is negligible for the drain voltage variation. With our underetching technique also device structures with self-aligned buried gate and channel length below 0.4 µm are fabricated on polymer substrates.

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