Caltech Nanofabrication Group

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Home Classes APh 9

Solid-State Electronics for Integrated Circuits (APh/EE 9)

Solid-State Electronics for Integrated Circuits

Winter 2013

 

Lecture Tuesdays 1-2pm
Thursdays 1-2pm
070 Moore
Lab 060 Moore, Time TBD
Office Hours Tuesdays 12-1pm
070 Moore
Prof. Axel Scherer
x4691, 203 Sloan Annex
Kent Potter Lab Equipment coordinator

x3886, 439 Moore
Erika Garcia
Grader

Kate Finigan Administrative Assistant

x4585, 212 Sloan Annex

Homework Policies:

  • On-time homework:
    • Turn them in during lecture hours, typically by 2:00pm Thursday in class
  • Late homework:
    • No late homework allowed
    • There will be no extensions except for emergencies, in which case you should contact Prof. Scherer
  • Location:
    • Homework is due in class, NOT in Sloan Annex
  • Graded homework can either be picked up in class or in the OUT box outside of Prof. Scherer's office
  • The grade for passing differs every year, so turn in ALL your homework even if you are taking the class Pass/Fail. You will get an "E" (incomplete) if you miss homework, and you will have to make it up before ADD DAY of the following term.

 

Lab Policies:

  • Attendance to ALL labs is REQUIRED to pass the course (you will get an "F" if you miss labs, for both freshman and upperclassmen)
  • You CANNOT change lab sessions after labs have started
    There will be no exceptions unless there is a medical or other emergency
  • You need to have your pre-lab ready before your lab session
  • There will be NO make-up labs at the end of the term, so you will get an "F" if you miss labs, unless there is an emergency (in which case, you should discuss with your TA to determine a time to make it up

 

Exams:

  • Midterm:
    To be announced
  • Final:
    To be announced
  • The exams will be open your own notes, lab manual, and the class textbook

 

Collaboration:

  • Homework:
    You may discuss the questions, but you must turn in your own work.
  • Labs:
    You must perform all steps to make and test your own device, with the exception of certain steps which happen in groups (oxidation and diffusion furnaces, HF etching, etc.)
  • Exams:
    You may not discuss the questions or collaborate at all.

 

Grading Policies:

  • Attendance to ALL labs will determine that you will not get an "F", but will not guarantee that you will automatically pass the course if you are taking it Pass/Fail (homework and exam grades will be taken into account as well)
  • Homeworks: 50%, Midterm: 20%, Final: 20%, Lab: 10%

 

How to make up an "E":

  • You will be asked to research on a topic (assigned by Prof. Scherer) that is related to semiconductor devices, and write a detailed report by Add Day of the following term

 


 

Lectures

 


 

Homeworks

  • Homework 1
    Posted: January 17, 2013
    Due: January 24, 2013
  • Homework 3
    Posted: January 31, 2013
    Due: February 7, 2013

 

Lab Schedule

The APh 9a labs begin the week of January 21, 2013.  The schedule is:

  • MOSFET
    Week of January 21, 2013
  • Project labs to follow

The TAs for the sections (subject to change) are:


Monday Tuesday Wednesday Thursday Friday Saturday
Afternoon
2-6pm
Aditya Rajagopal
No Section

No Section
No Section
No Section
Muhuammad Mujeeb-U-Rahman
Evening
7-11pm
William "Max" Jones
Dongwan Kim
Georgia Papadakis
Yu-Hung Lai
No Section

No Section
More in this category: Nanotechnology (EE/APh 180) »

Contact

Administrative and Financial Contact

Kate Finigan
MC 200-36, Caltech
1200 E California Blvd
Pasadena, CA 91125

Office:  212 Sloan Annex
Phone:  626.395.4585
Fax: 626.577.8442
Email: kate@caltech.edu

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