Caltech Nanofabrication Group

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Home Classes APh 9

Solid-State Electronics for Integrated Circuits (APh/EE 9)

Solid-State Electronics for Integrated Circuits

Fall 2016

 

Lecture Tuesdays 1-2pm
Thursdays 1-2pm
B270 Moore
Lab B260 Moore
Office Hours Contact your lab section TA for questions
Prof. Axel Scherer etcher@
x4691, 216 Powell-Booth
Kate Finigan Administrative Assistant
kate@
x4585, 215 Powell-Booth
Head TA Dvin Adalian
dvin@
x4671, 220 Powell-Booth
Grader TA Deepan Kumar
dkishore@
226 Powell-Booth MC 200-79

Homework Policies:

  • On-time homework/post-labs: Turn in during lab section
  • Late homework/post-labs: Half credit, turn in to grader TA mailbox
  • Graded homework can either be picked up in class or in the boxes outside of room 215 in Powell Booth. Boxes are marked
  • The grade for passing differs every year, so turn in ALL your homework even if you are taking the class Pass/Fail. You will get an "E" (incomplete) if you miss homework, and you will have to make it up before ADD DAY of the following term.

 

Lab Policies:

  • Attendance to ALL labs is REQUIRED to pass the course (you will get an "F" if you miss labs, for both freshman and upperclassmen)
  • You CANNOT change lab sessions after labs have started
    There will be no exceptions unless there is a medical or other emergency
  • You need to have your pre-lab ready before your lab session
  • There will be NO make-up labs at the end of the term, so you will get an "F" if you miss labs, unless there is an emergency (in which case, you should discuss with your TA to determine a time to make it up

 

Exams:

  • Midterm:
  • Final: There will be a 2-hour take-home open-book exam
  • The exams will be open your own notes, lab manual, and the class textbook

Prelabs and ReportS:

  • Prelab Format:
  • Purpose of the lab: State the device that you will be making, and the materials (e.g. GaAs or Si substrate, n-or p-doped, or undoped, the type of metal you’ll be depositing, etc) you’ll be using to make it.
  • Description of the device: Explain how the device works (in words, and maybe some equations as well).
  • Procedures: State briefly in words the fabrication process, and draw schematic diagrams (cross-sectional views) next to the description.
  • Measurements: What type of measurements you will be doing (e.g. IV characteristics, CV curves, etc), and what programs in the Agilent analyzers you will be using to take each of the measurements.
  • Calculations: These are found at the end of each lab in the APH9 laboratory manual (not all labs require calculations). For the ones that do, you need to figure out what equations to use for the calculations
  • Lab Write-ups:
  • You will need to turn in your pre-lab, measurements (plots), and calculations at the following lab session. Extensions may be given with your TA’s approval.

 

Collaboration:

  • Homework:
    You may discuss the questions, but you must turn in your own work.
  • Labs:
    You must perform all steps to make and test your own device, with the exception of certain steps which happen in groups (oxidation and diffusion furnaces, HF etching, etc.)
  • Exams:
    You may not discuss the questions or collaborate at all.

 

Grading Policies:

  • Attendance to ALL labs will determine that you will not get an "F", but will not guarantee that you will automatically pass the course if you are taking it Pass/Fail (homework and exam grades will be taken into account as well)
  • Homeworks/Postlabs: 50%, Final: 25%, Lab: 25%

 

How to make up an "E":

  • You will be asked to research on a topic (assigned by Prof. Scherer) that is related to semiconductor devices, and write a detailed report by Add Day of the following term




Monday Tuesday Wednesday Thursday Friday Saturday
Afternoon
2-6pm

Dvin Adalian
dvin@
Cat Le
cle@
Cat Le
cle@

Evening
7-11pm

Dvin Adalian
dvin@

Sith D.
sdomrong@
Lei Xia
lxia@

 


 

LAB SCHEDULE

The APh 9a labs begin the week of October 10th, 2016.

The lab manual is available here: APh 9 Lab Manual 2014 Revision

  • Semiconductor Materials
    Week of October 10th, 2016
  • Schottky Diode
    Week of October 17th, 2016
  • MOS Capacitor
    Week of October 24th, 2016
  • PN Diode Part 1
    Week of October 31st, 2016
  • PN Diode Part 2
    Week of November 7th, 2016
  • MOSTFET Part 1
    Week of November 14th, 2016
  • MOSEFT Part 2
    Week of November 28th, 2016

The APh 9b labs begin the week of April 11th, 2017.  The schedule is tenatively:

  • PV Cell
    Week of April 11th, 2017
  • BJT Part 1
    Week of April 18th, 2017
  • BJT Part 2
    Week of April 25th, 2017
  • Microfluidics Part 1
    Week of May 2nd, 2017
  • Microfluidics Part 2
    Week of May 9th, 2017
  • TBD
    Week of May 16th, 2017
  • TBD
    Week of May 23rd, 2016

Spring TERM 2015:

LECTURES

Fall Term 2013:

Lectures

Winter Term 2014:

lectures:

videos

FALL TERM 2013:


 

quiz sets / homeworks sets

  • TBA
More in this category: Nanotechnology (EE/APh 180) »

Contact

Administrative and Financial Contact

Kate Finigan
MC 200-79, Caltech
1200 E California Blvd
Pasadena, CA 91125

Office:  215 Powell-Booth
Phone:  626.395.4585
Fax: 626.577.8442
Email: kate@caltech.edu

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