Caltech Nanofabrication Group

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Home Classes APh 9

Solid-State Electronics for Integrated Circuits (APh/EE 9)

Solid-State Electronics for Integrated Circuits

Fall 2017

 

Lecture Tuesdays and Thursdays 1-2pm
B270 Moore
Lab B260 Moore
Office Hours Contact your lab section TA for questions
Prof. Axel Scherer etcher@
x4691, 216 Powell-Booth
Kate Finigan Administrative Assistant
kate@
x4585, 215 Powell-Booth
Head TA Dvin Adalian
dvin@
x4671, 220 Powell-Booth
Grader TA Dvin Adalian
dvin@
x4671, 220 Powell-Booth

Lecture Policies:

Lecture attendance is encouraged to get the most out of this course and to keep informed of potential schedule revisions.

Please limit use of electronics to academic purposes.

Food and drink are allowed but please limit disruption and clean up after yourself.

Pre and Post-lab Homework Policies:

No late assignments will be accepted other than for emergencies.  For emergencies contact both Professor Scherer & the head TA.

Graded homework can be picked up in class or by making arrangements with the head TA.

Must show work and write legibly (typed preferred) for credit

Pre and Post-lab Assignments:

Prelab Format:  Unless otherwise stated, the format is as follos:

o Purpose of the lab: State the device that you will be making, and the materials (e.g. GaAs or Si substrate, n-or p-doped, or undoped, the type of metal you’ll be depositing, etc) you’ll be using to make it.

o Description of the device: Explain how the device works (in words, and maybe some equations as well).

o Procedures: State briefly in words the fabrication process, and draw schematic diagrams (cross-sectional views) next to the description.

o Measurements: What type of measurements you will be doing (e.g. IV characteristics, CV curves, etc)

o Calculations: These are found at the beginning and end of each lab in the APh9 laboratory manual or provided by the TA (not all labs require calculations). For the ones that do, you need to figure out what equations to use for the calculations

Lab Write-ups: Unless otherwise stated:

o You will need to turn in your measurements (plots), and calculations/answers at the following lab session.   Extensions may be given with the head TA’s approval.

Lab Policies:

Lab sign-ups will take place during the second week of the term.  You cannot change lab sections after labs have started so figure out your schedule early.  Lab sections will be limited by TA schedules and are usually offered in the afternoons and/or evenings.

If you don’t already have after-hours access to Moore you can email Carol Sosnowski at and ask her nicely to add your UID #.

Closed-toed shoes and full length pants are required to attend lab.  You will have to go change if you forget.

Both the current pre and prior post labs are due at the start of lab.  No late pre/post labs will be accepted.  See current edition lab manual for pre and post lab assignments for each lab.

If you are sick let your lab TA and the head TA know as soon as possible to try and set you up in another section (please note this is very inconvenient).  Completion of all labs is required to pass this course. For emergency conflicts contact both Professor Scherer & the head TA.

Exam Policies:

Students will be allowed one 8.5” x 11” sheet of handwritten notes (front & back)

Graphing & scientific calculators only (no cell phone calculators or other electronics)

Must show work and write legibly for credit

Collaboration Policy:

Homework & Pre/Post Labs: You may discuss the questions & check answers, but you must turn in your own work. (do not copy or let others copy)

Labs: You must perform all steps to make and test your own device, with the exception of certain steps which happen in groups (oxidation and diffusion furnaces, HF etching, etc.).

Exams: You may not discuss the questions or collaborate at all.

Grading Policy:

Completion of all labs is required to pass this course

No late work will be accepted

Pre & Post Lab Assignments: 70%, Lab Participation: 10%, Final: 20%

 


Monday Tuesday Wednesday Thursday Friday Saturday
Afternoon
2-6pm

Lucia de Rose
lderose@



Evening
7-11pm
Steven Li
sli3@
Richard Smith
rdsmith@
Deepan Kumar
dkishore@



 

 


 

LAB SCHEDULE 2017

The APh 9a labs begin the week of October 9th, 2017

The lab manual is available here: APh 9 Lab Manual 2017 Revision

  • Semiconductor Materials Prelab Assignment and Procedures or Section 5.10 of the manual
    Week of October 9th, 2017
  • Schottky Diode, Section 5.2
    Week of October 16th, 2017
  • MOS Capacitor
    Week of October 23th, 2017
  • PN Diode Part 1
    Week of October 30st, 2017
  • PN Diode Part 2
    Week of November 6th, 2017
  • MOSTFET Part 1
    Week of November 13th, 2017
  • MOSEFT Part 2
    Week of November 27th, 2017

 


 

LAB SCHEDULE 2016

The APh 9a labs begin the week of October 10th, 2016.

The lab manual is available here: APh 9 Lab Manual 2014 Revision

  • Semiconductor Materials
    Week of October 10th, 2016
  • Schottky Diode
    Week of October 17th, 2016
  • MOS Capacitor
    Week of October 24th, 2016
  • PN Diode Part 1
    Week of October 31st, 2016
  • PN Diode Part 2
    Week of November 7th, 2016
  • MOSTFET Part 1
    Week of November 14th, 2016
  • MOSEFT Part 2
    Week of November 28th, 2016

The APh 9b labs begin the week of April 11th, 2017.  The schedule is tenatively:

  • PV Cell
    Week of April 11th, 2017
  • BJT Part 1
    Week of April 18th, 2017
  • BJT Part 2
    Week of April 25th, 2017
  • Microfluidics Part 1
    Week of May 2nd, 2017
  • Microfluidics Part 2
    Week of May 9th, 2017
  • TBD
    Week of May 16th, 2017
  • TBD
    Week of May 23rd, 2016

Spring TERM 2015:

LECTURES

Fall Term 2013:

Lectures

Winter Term 2014:

lectures:

videos

FALL TERM 2013:


 

quiz sets / homeworks sets

  • TBA
More in this category: Nanotechnology (EE/APh 180) »

Contact

Administrative and Financial Contact

Kate Finigan
MC 200-79, Caltech
1200 E California Blvd
Pasadena, CA 91125

Office:  215 Powell-Booth
Phone:  626.395.4585
Fax: 626.577.8442
Email: kate@caltech.edu

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