Caltech Nanofabrication Group

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Home Classes APh 9

Solid-State Electronics for Integrated Circuits (APh/EE 9)

Solid-State Electronics for Integrated Circuits

Fall 2015 / Spring 2016

 

Lecture Tuesdays 3-4pm
Thursdays 3-4pm
105 Annenberg
Lab 060 Moore
Office Hours Contact your lab section TA for questions
Prof. Axel Scherer etcher@
x4691, 203 Sloan Annex
Kate Finigan Administrative Assistant
kate@
x4585, 212 Sloan Annex
Head TA Max Jones
williamj@
x2749, 202 Sloan Annex
Grader TA Bassam Helou
bhelou@

Homework Policies:

  • On-time homework:
    • Turn them in during lecture hours, typically by 2:00pm Thursday in class or as instructed by Professor Scherer
  • Late homework:
    • No late homework allowed
    • There will be no extensions except for emergencies, in which case you should contact Prof. Scherer or your TA
  • Location:
    • Homework is due in class, NOT in Sloan Annex
  • Graded homework can either be picked up in class or in the boxes outside of room 209 in Sloan Annex. Boxes are marked
  • The grade for passing differs every year, so turn in ALL your homework even if you are taking the class Pass/Fail. You will get an "E" (incomplete) if you miss homework, and you will have to make it up before ADD DAY of the following term.

 

Lab Policies:

  • Attendance to ALL labs is REQUIRED to pass the course (you will get an "F" if you miss labs, for both freshman and upperclassmen)
  • You CANNOT change lab sessions after labs have started
    There will be no exceptions unless there is a medical or other emergency
  • You need to have your pre-lab ready before your lab session
  • There will be NO make-up labs at the end of the term, so you will get an "F" if you miss labs, unless there is an emergency (in which case, you should discuss with your TA to determine a time to make it up

 

Exams:

  • Quizzes: There will be an in-class 10 minute quiz most Thursdays, remember to attend.
  • Midterm:
  • Final:
  • The exams will be open your own notes, lab manual, and the class textbook

Prelabs and ReportS:

  • Prelab Format:
  • Purpose of the lab: State the device that you will be making, and the materials (e.g. GaAs or Si substrate, n-or p-doped, or undoped, the type of metal you’ll be depositing, etc) you’ll be using to make it.
  • Description of the device: Explain how the device works (in words, and maybe some equations as well).
  • Procedures: State briefly in words the fabrication process, and draw schematic diagrams (cross-sectional views) next to the description.
  • Measurements: What type of measurements you will be doing (e.g. IV characteristics, CV curves, etc), and what programs in the Agilent analyzers you will be using to take each of the measurements.
  • Calculations: These are found at the end of each lab in the APH9 laboratory manual (not all labs require calculations). For the ones that do, you need to figure out what equations to use for the calculations
  • Lab Write-ups:
  • You will need to turn in your pre-lab, measurements (plots), and calculations at the following lab session. Extensions may be given with your TA’s approval.

 

Collaboration:

  • Homework:
    You may discuss the questions, but you must turn in your own work.
  • Labs:
    You must perform all steps to make and test your own device, with the exception of certain steps which happen in groups (oxidation and diffusion furnaces, HF etching, etc.)
  • Exams:
    You may not discuss the questions or collaborate at all.

 

Grading Policies:

  • Attendance to ALL labs will determine that you will not get an "F", but will not guarantee that you will automatically pass the course if you are taking it Pass/Fail (homework and exam grades will be taken into account as well)
  • Homeworks: 50%, Midterm: 20%, Final: 20%, Lab: 10%

 

How to make up an "E":

  • You will be asked to research on a topic (assigned by Prof. Scherer) that is related to semiconductor devices, and write a detailed report by Add Day of the following term

 


Spring TERM 2015:

LECTURES

Fall Term 2013:

Lectures

Winter Term 2014:

lectures:

videos

FALL TERM 2013:


 

quiz sets / homeworks sets

  • TBA

 

Lab Schedule

The APh 9a labs begin the week of October 12th, 2015.

  • Semiconductor Materials
    Week of October 12th, 2015
  • Light Emitting Diode
    Week of October 19th, 2015
  • Schottky Diode
    Week of October 26th, 2015
  • MOS Capacitor
    Week of November 2nd, 2015
  • PN Diode
    Week of November 9th, 2015
  • Microfluidics Part 1
    Week of November 16th, 2015
  • Microfluidics Part 2
    Week of November 30th, 2015

The APh 9b labs begin the week of January 20, 2016.  The schedule is tenatively:

  • Silicon Photovoltaic/Photodiode
    Week of January 20, 2016
  • Laser Resonator
    Week of January 27, 2016
  • MOSFET
    Week of February 3, 2016
  • BJT
    Week of February 17, 2016

Monday Tuesday Wednesday Thursday Friday Saturday
Afternoon
2-6pm

Sith D.
sdromrong@
Dvin Adalian
dvin@
W. "Max" Jones
williamj@


Evening
7-11pm
Keith Russell
krussell@
Yu-Hung
ylai@

Yu-Hung
ylai@
Keith Russell
krussell@

More in this category: Nanotechnology (EE/APh 180) »

Contact

Administrative and Financial Contact

Kate Finigan
MC 200-36, Caltech
1200 E California Blvd
Pasadena, CA 91125

Office:  212 Sloan Annex
Phone:  626.395.4585
Fax: 626.577.8442
Email: kate@caltech.edu

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