Policies Lectures Homeworks Lab schedule		APh 9b Solid-State Electronics for Integrated Circuits Winter 2009 Lecture Tuesdays 1-2pm, Thursdays 1-2pm 070 Moore Lab 060 Moore, Time TBD Prof Axel Scherer etcher at caltech dot edu x4691, rm 203 Sloan Annex Kent Potter Lab coordinator potter at caltech dot edu x3886, 439 Moore Kate Finigan Adm. Assistant kate at caltech dot edu x4585, rm 212 Sloan Annex Homework Policies: On-time homework: Turn them in during lecture hours, typically by 2:00pm Thursday in class Late homework: No late homework allowed There will be no extensions except for emergencies, in which case you should contact Prof. Scherer Location: Homework is due in class, NOT in Sloan Annex Graded homework can either be picked up in class or in the OUT box outside of Prof. Scherer's assistant's office The grade for passing differs every year, so turn in ALL your homework even if you are taking the class Pass/Fail. You will get an "E" (incomplete) if you miss homework, and you will have to make it up before ADD DAY of the following term. Lab Policies: Attendance to ALL labs is REQUIRED to pass the course (you will get an "F" if you miss labs, for both freshman and upperclassmen) You CANNOT change lab sessions after labs have started There will be no exceptions unless there is a medical or other emergency You need to have your pre-lab ready before your lab session There will be NO make-up labs at the end of the term, so you will get an "F" if you miss labs, unless there is an emergency (in which case, you should discuss with your TA to determine a time to make it up Exams: There will be a 1-hour in-class written exam and a 3-hour take-home final (dates will be announced in class) The exams will be open your own notes, lab manual, and the class textbook Grading Policies: Attendance to ALL labs will determine that you will not get an "F", but will not guarantee that you will automatically pass the course if you are taking it Pass/Fail (homework and exam grades will be taken into account as well) Homeworks: 50%, Midterm: 20%, Final: 20%, Lab: 10% How to make up an "E": You will be asked to research on a topic (assigned by Prof. Scherer) that is related to semiconductor devices, and write a detailed report by Add Day of the following term Lectures Lecture 1 Drift and diffusion, oxidation, implantation, vacuums Lecture 2 Vacuums (continued), metalization, etching Lecture 3 Lecture 4 Lecture 5 Lecture 6 Lecture 7 Homeworks Pick up in class on Thursdays. Lab Schedule The APh 9b lab schedule is: Lab Weeks Pages The TAs for the sections are: Monday Tuesday Wednesday Thursday Friday Afternoon 2-6pm No Section Dave Henry mdhenry at caltech dot edu Andrew Homyk homyk at caltech dot edu No Section No Section Evening 7-11pm No Section No Section Kee Scholten keedude at caltech dot edu Tom Gwinn tgwinn at caltech dot edu Imran Malik imran at caltech dot edu